Phase locked loops (“PLL”) have been used extensively in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced in more general digital electronic circuits. For example, application specific integrated circuits (“ASIC”) used in a variety of circuit applications typically include on-chip PLLs for clock signal distribution.
The key advantages that PLLs bring to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL enables one periodic signal or clock signal to be phase-aligned to frequency multiples of a reference clock signal. As the name implies, the output of the PLL locks onto the incoming reference clock signal and generates a periodic output signal with a frequency substantially equal to the average frequency of the reference clock. When the output PLL signal tracks the reference signal, the PLL is said to be “locked.”
A PLL, however, will only remain locked over a limited frequency range or shift in frequency called a hold-in or lock range. The PLL generally tracks the reference signal over the lock range, provided the reference frequency changes slowly. If the frequency changes at too fast of a rate, the PLL will drop out of lock. The maximum rate of change of the reference frequency (without loosing lock) is known as the “locked sweep rate.”
PLLs are typically designed for a specific frequency range. A voltage controlled oscillator (VCO) along with a charge pump are used to create a waveform output. The frequency of the waveform output is directly dependent on the circuit components within the voltage controlled oscillator and/or charge pump. These circuit components often include gain elements such as a differential amplifier. The gain of a differential amplifier (or other gain elements) is limited to a specific voltage range. When a voltage is applied to a differential amplifier that is outside of its normal operating range, the gain of the differential amplifier may become too reduced to be useful. Addtionally, operating outside of the differential amplifier's normal voltage range may lead to instability in the operation of the differential amplifier. This instability may the result in operational instability in an associated VCO and/or PLL.
Because differential amplifiers and related circuitry are limited to a specific voltage range, the useful output range of a corresponding VCO is likewise limited to a specific frequency range and the frequency range of a PLL in which such a VCO is implemented is accordingly limited to the specific frequency range of the VCO. For example, FIG. 1a illustrates frequency output vs. input voltage for a VCO (exerpt from “A Low-Noise, 900-MHz VCO in 0.6 μm CMOS”, IEEE Journal of Solid State Electronics, May 1999, p 586-191). In this example, the normal operating gain is 300 MHz/V in an input voltage range of 1.4-1.8V. Input voltages in the range of 1-1.3 V may have a gain of 450 MHz/V. Higher input voltages, for example, 2.2-2.4 V, may produce a reduced gain of 200MHz/V. Because the stability of a PLL is directly related to the gain of the PLL, it is important to consider the gain of the PLL for a given output frequency of the VCO. If the gain varies, the stability of the PLL may therefore vary.
It is desirable for a PLL to have a wide frequency range. Some advantages of a wide frequency range include a large spectrum of output frequencies and ease of integration into various components and/or devices. A large spectrum of output frequencies allows a single PLL to produce a desired waveform for an application that may use a broad range of frequencies. If a PLL has a narrow bandwidth, however, two or more PLLs may be required in a specific application. For semiconductor devices, adding on chip PLLs increases the area of a chip, power consumption, and static current, which is undesirable.
PLLs with large bandwidths are desirable because such PLLs may be provided as standard parts or standard design cells. For instance, instead of providing mulitiple PLLs in a design library, a single large bandwidth PLL may be provided. Such a PLL may then be combined with other circuits without the overhead of designing a specific PLL for each specific application.
Conventional methods of increasing the bandwith of a PLL include adding dividers to the PLL feedback path and adjusting current to the charge pump feeding the VCO. While adding dividers in the PLL feedback loop does increase the output frequency of the PLL, as discussed above, the gain of the PLL will vary depending on the output frequency range. This variation in gain of the PLL presents integration issues when covering a wide frequency range. Additionally, instability of the PLL may also result from such variation in gain.
Adjusting the current output of a charge pump, as disclosed in U.S. Pat. No. 6,710,670 (Maneatis), may also provide for improving an operating frequency range of a PLL. In Maneatis, a feedback path from a bias generator is used to adjust the amount of current output from the charge pump. However, several complications arise in this method. Integration of the charge pump requires a more complicated loop filter (for impedence matching). Also, when the PLL is operated over a large frequency range, inadvertant noise created by the charge pump may occur. Overall, the more complicated loop filter makes fabricating the PLL more difficult. In addition, adjusting the PLL over a wide frequency range is also more complicated.
PLLs including a VCO that has a stable gain over a wide frequency range, however, would provide more flexibility in the design and integration of such PLLs with other circuits. Therefore, there is a need for an improved VCO that has a stable gain over a wide frequency range.